| 摘要 |
<p>A serial communication system (35) for two IC devices (43 and 45) has a separate master chip (41) connected to both of the IC devices, the master chip having a clock generator (51) and circuitry for affecting serial data transmission and control between the master chip and the IC devices. There is a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment each slave periodically checks phase between data stream and clock stream received, and inserts a correction code in the data stream sent back to the master chip, so the master chip can regularly correct the phase for clock and data sent to each slave.</p> |
