| 摘要 |
In one aspect the present invention provides for a method for executing a sequence of instructions in a processor. The method comprises decoding a first the instructions into one or more first micro-ops, renaming destination registers identified in a first portion of the first micro-ops by reassigning available additional physical registers for the destination registers, and decoding a second portion of the first micro-ops into one or more second micro-ops. The act of renaming has renamed a destination register of at least one micro-op of the second portion of the first micro-ops. The method executes a third portion of the first and the second micro-ops.
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