| 摘要 |
In a clock reproducing circuit for use in a multilevel QAM demodulation circuit and including a clock phase error detecting circuit receiving a digital in-phase signal to generate a phase error signal, and a voltage controlled oscillator receiving the phase error signal through a loop filter, for generating a reproduced clock, the clock phase error detecting circuit comprises first and second delay circuits receiving the digital in-phase signal, the first delay circuit generating a ½-data period delayed signal, and the second delay circuit generating a one-data period delayed signal; an offset value generating circuit receiving the in-phase signal and the one-data period delayed signal for generating an offset value; a first subtracting circuit for subtracting the offset value from the ½-data period delayed signal to generate a first phase error signal; a second subtracting circuit for subtracting the one-data period delayed signal from the in-phase signal to generate a subtraction result signal; a sign inverting circuit for selectively inverting the sign of the first phase error signal on the basis of the subtraction result signal, to output a second phase error signal; a first discriminating circuit for comparing the subtraction result signal with a first threshold to output a first discrimination result signal; an addition circuit for adding the one-data period delayed signal to the in-phase signal to generate an addition result signal; a second discriminating circuit for comparing the addition result signal with a second threshold to output a second discrimination result signal; and a gate circuit controlled by the first and second discrimination result signals either to output the second phase error signal as the phase error signal or output a held signal as the phase error signal.
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