发明名称 |
Fully self-aligned method for fabricating transistor and memory |
摘要 |
A fully self-aligned method for fabricating a transistor is described. The source/drain contact opening is formed in the forming step of the gate to avoid the problem of misalignment. Therefore, the complex processes and the poly pad layer of the conventional method are not needed. A fully self-aligned method for fabricating memory is described. The memory cell and logic circuit regions have the same height during the formation process of the memory.
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申请公布号 |
US6190958(B1) |
申请公布日期 |
2001.02.20 |
申请号 |
US19990293430 |
申请日期 |
1999.04.16 |
申请人 |
UNITED SEMICONDUCTOR CORP. |
发明人 |
CHUANG SHU-YA |
分类号 |
H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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