发明名称 |
System and method for comparing values during logic analysis |
摘要 |
Disclosed is a system and method to compare logical values. The system employs a field programmable gate array (FPGA) configured for comparing logical values. The FPGA includes a number of inputs to receive an N-bit sampled value from a target system, where N defines the number of bits in the N-bit sampled value. The FPGA also includes a number of lookup tables configured to receive an M-bit portion of the N-bit sampled value. These lookup tables generate a lookup table output in response to the M-bit portion. Finally, an AND operation is performed on the outputs of the lookup tables that generates an output indicating whether the particular N-bit logical value matches a particular desired value. Note that a single AND gate may be used or a number of AND gates may be used in place of the single AND gate. The tables within the lookup tables are generated based upon a desired logical value and a comparison mask value.
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申请公布号 |
US6191683(B1) |
申请公布日期 |
2001.02.20 |
申请号 |
US19990386614 |
申请日期 |
1999.08.31 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
NYGAARD, JR. RICHARD A. |
分类号 |
G06F7/02;(IPC1-7):G05B1/00 |
主分类号 |
G06F7/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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