| 摘要 |
PURPOSE: A reference clock generating circuit is provided to be capable of generating a plurality of reference clocks using a phase mixer without utilizing a feedback loop. CONSTITUTION: A quadrature generator(10) amplifies a clock input signal(CLKIN) to output clock signals(CLK1, CLK2, CLK1b, CLK2b) having a phase difference of 90 deg. to each other. The quadrature generator(10) includes the first amplifier for generating the clock signals(CLK1, CLK1b) in response to the clock input signal(CLKIN) and an inverted version of the clock input signal, a delay part for delaying the clock input signal(CLKIN) and an inverted version of the clock input signal by 90 deg respectively, and the second amplifier for generating the clock signals(CLK2, CLK2b) in response to the clock input signal(CLKIN) and an inverted version of the clock input signal. The first to fourth phase mixers(20-50) receive the clock signals(CLK1, CLK2, CLK1b, CLK2b) to output reference clock signals(K4, K4b), (K1, K1b), (K2, K2b), and (K3, K3b).
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