| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the capacity of a data memory without increasing a reading rate. SOLUTION: This device is provided with a data memory 11 storing M pieces of N-bit parallel data, a fraction bit memory 12 storing fraction bit parallel data, an address counter 17 designating each address of the M pieces of N-bit parallel data outputted from the memory 11 in turn, a multiplexing circuit 16 converting the parallel data into serial data, a switching circuit 15 switching a parallel data inputted to the circuit 16 from the N-bit parallel data into fraction bit parallel data in accordance with a switching command, and a switching control circuit 18 which transmits a switching command for as much as time needed for the fraction bit parallel data to be outputted as a serial data signal to the circuit 15 after the address counter finishes designating the addresses of the M pieces of N-bit parallel data and restarts the address counter after the transmission.</p> |
