| 摘要 |
PROBLEM TO BE SOLVED: To realize a semiconductor integrated circuit which can be protected against timing violations, restraining it from increasing in scale. SOLUTION: No restrictions as to a hold time violation are given, but restrictions as to a setup time violation are given, when a logic is synthesized. Timing analysis of a net list is conducted, and when a hold time violation is detected in a path between FF circuits 8 and 11, the FF circuit 8 or the FF circuit 11 is replaced by a modifying FF circuit unit 12. The modifying FF circuit unit 12 is equipped with delay circuits 13, which are each positioned before a data input terminal and after a data output terminal, previously turned to a unit type, minimized in cell area, and registered in a library.
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