| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce probability in which a flash cell is made an over-erasing state from an erasing operation state by equalizing substantially erasing speed characteristics of a flash cell before erasing operation, and reducing possibility of occurrence of an over-erasing flash cell. SOLUTION: A main task in a previous erasing process is to reduce an electric field relating to a tunneling oxide for the bit and to perform quick bit correction of a non-volatile flash array memory. When an electric field relating to a tunneling oxide is made larger, electric charges integration or discharge rate for a floating gate of a cell is made larger, too. Therefore, when an electric field of a tunneling oxide is reduced so as to have a high initial start electric field value by advance of erasing operation, speed of the cell is decreased, it performs behavior being nearer to a target cell during past erasing operation. Consequently, erasing speed of whole memory array cells are equalized in meaning of that high speed bits are adapted so as to resemble to residual of cell population.</p> |
