| 摘要 |
PROBLEM TO BE SOLVED: To realize high speed transmission in a CMOS LSI by reducing the phase difference among a plurality of data by a correction circuit consisting of a fixed pattern generating means, a variable delaying means and a simple digital circuit. SOLUTION: The phase of data is detected by performing retiming of the data by a delayed clock, and phase difference between data is reduced in such a manner that a correcting and controlling means 12 corrects the delay quantity of data. Subsequently, a transmitting side selector 6 outputs optional data from internal logic, and a receiving side flip-flop 11 fetches the data. |
