| 摘要 |
PROBLEM TO BE SOLVED: To eliminate misrecognition when a data signal synchronized with a high-speed clock is processed at the time of the input of the data signal. SOLUTION: This device 1 has a data input terminal 2 where a data signal is inputted from outside, a clock input terminal 3 where a clock is inputted from outside, and a D flip-flop circuit 4 which is supplied with the data signal from the data input terminal 2 and the clock from the clock input terminal 3. Then the data signal sent out of the D flip-flop circuit 4 is sent out to a signal processing circuit 6 which operates in synchronism with the clock sent out of a trafling-stage clock tree 5 to prevent the signal processing circuit 6 from misrecognizing the data signal. |
