| 摘要 |
<p>PROBLEM TO BE SOLVED: To stably generate a reset signal, regardless of power-on by toggling a voltage level from high to low, before the voltage of a signal outputted by inputting a power-on signal is boasted to a desired voltage level and generating a power-on reset signal in response to the voltage level. SOLUTION: An input part 410 inputs an external circuit power-on signal P-ON by using a P/NMOS transistor, diminish influence and generates the signal of an output node N41. A Schmitt trigger inverter 430 generates the signal of an output node N45, which is inverted from the signals of the output nodes N41 and N44 in the input part 410. A reset signal generating part 450 outputs the power-on reset signal POR, whose pulse width is decided by a delay element 455 and an exclusive OR gate XOR41, in response to the signal of the output node N45 in the inverter 430. Thus, the reset signal is stably generated, regardless of the turn-on timing of power.</p> |
