RECEPTION METHOD AND RECEIVER FOR START-STOP SYNCHRONOUS COMMUNICATION

摘要

PROBLEM TO BE SOLVED: To apply a plurality of transfer conditions different from that of accurate reception processing to a start-stop synchronous reception system where a transfer condition is recognized from received data whose transfer condition is not clear. SOLUTION: Every time a start bit detection circuit AC recognizes a start bit denoting a head of a character of received data 00, a start bit length register AD measures the bit length and a CPU B recognizes it as a transfer rate. In the meantime, a sampling timer AE receives the start bit length and generates a sampling clock 19 placed in the center after a succeeding bit by using a 1/2 bit length for a start point. A reception buffer AH temporarily stores data sampled by the clock 19 via an input shift register AG. Various conditions such as a character length, presence/absence of the parity, an odd/even parity and a stop bit length are recognized by a bit pattern of an AT command read from a reception buffer AH by the CPU B, and they are set to a reception control section D with the transfer rate. The reception buffer AH is switched to a serial output and outputs stored reception data to a reception control section D.