| 摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM of a multi-level that the space is not so occupied, the manufacturing cost is reduced, and yield is improved. SOLUTION: A memory cell of quaternary is arranged at an intersection of a word line WL and a sub-bit line BLNx. Potentials corresponding to 11/10/01/00 are written in a dummy cell arranged at an intersection of a dummy word line DWLN/T and a sub-bit line connected to SSA 31, 32. A SSA 30 outputs data of a memory cell and a reference level of 0x/1x on a sub-bit line to main bit lines GBLN0, GBLT0. The SSA 31 outputs a reference level of 11/10 to a main bit line GBLN4 by balancing potentials of dummy cells connected to both dummy word lines. Similarly, the SSA 32 outputs a reference level of 01/00 to a main bit line GBLT4 by balancing potentials of both dummy cells. A MSA33 discriminates upper bits UPBIT/lower bits LWBIT of data based on potentials on four main bit lines.
|
