发明名称 LOGIC VERIFYING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a logic verifying system for improving and making uniform quality of logic verification for pointing out a fault by automatically executing optimized test menus hierarchically arranged on the basis of analysis of error contents when that error is detected. SOLUTION: Tests selected out of a test group 100 are prepared as test menus 201a-203a optimized corresponding to respective hierarchies. According to these prepared test menus 201a-203a, the tests classified into groups are executed. When any error is detected, the test menus 201c and 202c hierarchically arranged on the basis of the analysis of these error contents and optimized as tests by hierarchies are automatically executed. Thus, the optimal test can be executed for pointing out the logic fault without human intervention. Therefore, at the time point when the test is finished, a fault logic spot can be inferred.
申请公布号 JP2001043109(A) 申请公布日期 2001.02.16
申请号 JP19990218378 申请日期 1999.08.02
申请人 HITACHI LTD;HITACHI INFORMATION TECHNOLOGY CO LTD 发明人 KIYOTA KOICHIRO;KADOTA HIROSHI
分类号 G01R31/317;G06F11/22 主分类号 G01R31/317
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