发明名称 COMPUTER SYSTEM
摘要 PROBLEM TO BE SOLVED: To reduce the read latency of cache data when a cache tag part and a cache data part are divided and managed in a cache type computer system. SOLUTION: In memory read processing, a coherent controller 20 before reading a cache tag out of a cache tag part 5 and making a cache hit check, issues a discarding read request to preread (discarding read) data from a cache data part 7, to a cache data controller 6. The cache data controller 6 holds discarding-read data from the cache data part 7 and sends the discarding-read data back as reply dada once receiving a read request issued by the coherent controller 20 at the time of a cache hit.
申请公布号 JP2001043130(A) 申请公布日期 2001.02.16
申请号 JP19990216614 申请日期 1999.07.30
申请人 HITACHI LTD 发明人 SAKAKIBARA TADAYUKI;OHARA ISAO;AKASHI HIDEYA;TSUSHIMA YUJI;MURAOKA SATOSHI
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项
地址