| 摘要 |
PROBLEM TO BE SOLVED: To provide a FIFO circuit in which the number of buffers connected to each output port is decreased, parasitic capacity is reduced, and which can perform high speed operation. SOLUTION: This circuit has an input register 18 holding data inputted from plural input ports, a shifter 20 rearranging data from the input register, a shift register 24 holding and shifting data supplied from the shifter, a selector circuit 22 selecting output of the input register and the shift register so that effective data are filled successively from the lowest side, and a control circuit 26 controlling the input register, the shift register, the shifter, and the selector circuit. Thereby, the number of buffers connected to plural output ports respectively from the input register and the shift register in the selector circuit can be decreased, parasitic capacity of each output port can be reduced, and high speed operation can be performed.
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