发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To improve the yield and reliability of a semiconductor integrated circuit device by improving the planarity of an insulating film on metal interconnections formed by a CMP(Chemical mechanical polishing) method, and suppressing short circuits of the metal interconnections formed by the CMP method. SOLUTION: In a process step where a sacrificial film 16 is formed on an insulating film 11b and interconnections buried in grooves 15 formed of the films 11b and 16 are formed by deposition of a titanium nitride film 14b (barrier film) and a conductive film 18, such as a copper film and polishing using a CMP method, the film 16 which is polished at a speed higher than for the film 18 is polished at the same time. The film 16 is formed by implanting boron ions into the surface of the film 11b.
申请公布号 JP2001044201(A) 申请公布日期 2001.02.16
申请号 JP19990215646 申请日期 1999.07.29
申请人 HITACHI LTD 发明人 KONISHI NOBUHIRO;OKUDAIRA SADAYUKI;FUKADA SHINICHI
分类号 H01L21/3205;H01L21/28;H01L21/304;H01L21/768;H01L23/52;H01L23/522;(IPC1-7):H01L21/320 主分类号 H01L21/3205
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