| 摘要 |
Memory cell having a floating gate (41) with lateral edges (41a, 41b) which are aligned directly above edges (42a), (42b) of the active area (42) in the substrate (46), a control gate (43) positioned directly above the floating gate (41), and a select gate (44) spaced laterally from the control gate (43). The memory cell is fabricated by forming a poly-1 layer and an overlying dielectric film on a substrate in areas in which the stack transistors are to be formed, forming a poly-2 layer over the dielectric film and over areas of the substrate in which the select transistors are to be formed, patterning the poly-2 layer to form control gates for the stack transistors and select gates for the select transistors, removing the poly-1 layer and the dielectric film to form floating gates in areas which are not covered by the control gates, and forming source and drain regions in the substrate.
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