| 摘要 |
A multi-level discrete computer system (100) comprised of a central processing unit, CPU, (105) for processing multi-level discrete signals (mits), memory means (110) for storing multi-level mits of data, input means (115) for receiving mit data from external devices and forwarding said mit data to said central processing unit, output means (120) for receiving mit data from said central processing unit and forwarding said mit data to external devices, and bus lines carrying mit data for operatively connecting said central processing unit with said memory means, input means, and output means. The CPU includes an arithmetic logic unit (ALU) including logic gates, a register unit (150), and a control unit (155) for manipulating mits of data. The system also includes a level converter for converting mit data signals of a first base level to mit data signals of a second base level.
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