发明名称 DUAL PROCESS SEMICONDUCTOR HETEROSTRUCTURES AND METHODS
摘要 A method for forming an epitaxial layer (4) involves depositing a buffer layer (2) on a substrate (1) by a first deposition process, followed by deposition of an epitaxial layer (4) by a second deposition process. By using such a dual process, the first and second deposition processes can be optimized, with respect to performance, growth rate, and cost, for different materials of each layer. A semiconductor heterostructure prepared by a dual deposition process includes a buffer layer (2) formed on a substrate by MOCVD, and an epitaxial layer (4) formed on the buffer layer (2), the eptitaxial layer deposited by hydride vapor-phase deposition.
申请公布号 WO0063961(B1) 申请公布日期 2001.02.15
申请号 WO2000US09999 申请日期 2000.04.13
申请人 CBL TECHNOLOGIES, INC.;MATSUSHITA ELECTRONICS CORPORATION 发明人 SOLOMON, GLENN, S.;MILLER, DAVID, J.;UEDA, TETSUZO
分类号 C30B29/38;H01L21/205;H01L33/00;(IPC1-7):H01L21/31 主分类号 C30B29/38
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