| 摘要 |
PURPOSE: An apparatus for controlling packet transceiving processes is provided to implement a packet transceiving controller of a packet transceiving device, to transceive packets with memory writing/reading operations, and thereby simplifying operations of a processor to reduce load assignments of the processor and to perform a high speed of packet exchanges between internal processors of a base station. CONSTITUTION: A memory access unit(31) generates a control signal for accessing a dual port RAM(DPRAM)(21). A transmission controller(32) stores data of the DPRAM(21) in an internal transmission first-in-first-out(FIFO) unit(33) under control of the memory access unit(31). The transmission FIFO unit(33) buffers data for being transmitted to other processor under control of the transmission controller(32). A transmission terminal(34) allocates bytes to the data read from the transmission FIFO unit(33), to interface with an asynchronous transmission chip(23a), and generates a flag. A receiving terminal(37) interprets byte data received from an asynchronous receiving chip(23b) to process a related status, and stores the byte data in a receiving FIFO unit(38). The receiving FIFO unit(38) buffers receiving data under control of the receiving terminal(37). A receiving controller(22) controls a stream of the receiving data, to store information read from the receiving FIFO unit(38) in the DPRAM(21). A register controller(35) controls entire operations of the packet transceiving controller(22) under control of a processor(10). A clock distributor(36) distributes clocks to each device of the packet transceiving controller(22).
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