| 摘要 |
In order to prevent a through current from flowing to a set of MOS transistors in the final stage constituting a push-pull buffer circuit, a reset circuit which performs delaying operation and logic decision by separately receiving signals from two inverter gate groups of a control system and output system arranged in the preceding stage of the transistors is provided. Therefore, the flowing of the through current to the transistors can be prevented even when an input- output circuit consistinng of two power source systems becomes unstable when the power sources are turned on or off and such logic on which a through current flows to the final stage due to a signal output of a signal level converting circuit is generated because the rest circuit forcibly cancels the logic by applying feedback. |
