Method and apparatus for varying a clock frequency on a phase by phase basis

摘要

A circuit (218) to vary a frequency of an input clock (216) is disclosed. The circuit (218) includes a delay generator (310) to generate at least two delayed clocks (D1 and DM) from the input (216) clock and a select circuit (320) coupled to receive the at least two delayed clocks (D1 and DM) and provide an output clock (325) from one of the at least two delayed clocks (D1 and DM). The select circuit (320) switches the output clock from the one of the at least two delayed clocks to the other of the at least two delayed clocks on a first edge.