发明名称 |
METHOD FOR MANUFACTURING POWER DEVICE USING SLOPED ETCHING OF INSULATING LAYER |
摘要 |
PURPOSE: A fabrication method of a power device is provided to increase a reliability of a power device by preventing a breakage of an insulating layer due to a high electric field at a gate extended region. CONSTITUTION: A p-channel LDMOS(Lateral Double Diffused MOS) having a silicon gate pattern(15) is formed by depositing a gate low temperature insulating layer(12) on a first gate oxide layer(11). After forming a first gate oxide layer(11a) and the gate low temperature insulating layer(12) on the gate extended region, the first gate oxide layer(11a) and the gate low temperature insulating layer(12) is etched slightly by a wet etching process using a photoresist mask. After growing a second gate oxide layer(13), an n-channel LDMOS having a polysilicon gate pattern(15) is formed, thereby reducing a surface step coverage by etching a portion of the field oxide layer of the n-channel and the p-channel LDMOS devices during the wet etching process of the gate low temperature insulating layer.
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申请公布号 |
KR100289056(B1) |
申请公布日期 |
2001.02.14 |
申请号 |
KR19970070318 |
申请日期 |
1997.12.19 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
KOO, JIN GEUN;LEE, DAE U;NAM, GI SU;NOH, TAE MUN |
分类号 |
H01L29/78;(IPC1-7):H01L29/78 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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