发明名称 |
Performance monitoring of cache misses and instructions completed for instruction parallelism analysis |
摘要 |
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture. |
申请公布号 |
US6189072(B1) |
申请公布日期 |
2001.02.13 |
申请号 |
US19960767656 |
申请日期 |
1996.12.17 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LEVINE FRANK ELIOT;MOORE ROY STUART;ROTH CHARLES PHILIP;WELBON EDWARD HUGH |
分类号 |
G06F11/34;(IPC1-7):G06F12/10 |
主分类号 |
G06F11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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