发明名称 |
CVD plasma process to fill contact hole in damascene process |
摘要 |
The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
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申请公布号 |
US6187666(B1) |
申请公布日期 |
2001.02.13 |
申请号 |
US19990328148 |
申请日期 |
1999.06.08 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
SINGH BHANWAR;TEMPLETON MICHAEL K.;RANGARAJAN BHARATH;LYONS CHRISTOPHER F.;YEDUR SANJAY K.;SUBRAMANIAN RAMKUMAR |
分类号 |
H01L21/311;H01L21/312;H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/311 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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