发明名称 Method of forming self-aligned unlanded via holes
摘要 The present invention discloses a method of forming self-aligned unlanded via holes. First, a substrate having a patterned conductive layer on its surface is provided, and then a first dielectric layer is deposited on the substrate by using high density plasma chemical vapor deposition (HDP CVD). Next, a silicon nitride layer and a second dielectric layer are sequentially deposited on the first dielectric layer. Thereafter, the second dielectric layer, the silicon nitride layer and the first dielectric layer are etched back to remove a portion of the silicon nitride layer overlying the patterned conductive layer. Finally, a third dielectric layer is deposited, and then via holes are defined in the third dielectric layer.
申请公布号 US6187668(B1) 申请公布日期 2001.02.13
申请号 US19990347977 申请日期 1999.07.06
申请人 UNITED MICROELECTRONICS CORP. 发明人 WU HUA-SHU;PENG CHUN-HUNG;LIN HUNG-CHAN
分类号 H01L21/60;(IPC1-7):H01L21/476 主分类号 H01L21/60
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