| 摘要 |
A nonvolatile ferroelectric memory has a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines, and a reference bitline on one side of the plurality of bitlines. A cell array has a plural repetition of the plurality of bitlines and the reference bitline on one side thereof, a sense amplifier array having a plurality of sense amplifiers for sensing data on the bitlines and the reference bitlines in the cell array, a wordline and plateline driver for selective application of driving signals to the wordlines and the platelines, and a switching unit for selective turning on/off of the bitlines, the reference bitlines, and the input/output nodes on the sense amplifier array, whereby improving chip operation performance and lifetime of the chip.
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