| 摘要 |
A circuit arrangement for sensing errors in bit patterns for recording and plotting the occurrence in time, precisely to a bit, of transmission errors in a binary test signal. A pulse-generating device (5), which is fed a bit error signal sequence (BFS) generates a pulse (IS) in response to every signal change. A counting device (11), increments a counter as a function of a supplied bit timing (BT) and resets it to count value 1 when the pulse (IS) from the pulse-generating device (5) is applied. A buffer device (13) linked to the outputs of the counting device stores the counter contents of the counting device (11) in response to the application of a pulse (IS). An evaluation device (17,19,23) is fed, stores and displays the buffered counter contents.
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