发明名称 |
Integrated memory having column decoder for addressing corresponding bit line |
摘要 |
The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.
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申请公布号 |
US6188642(B1) |
申请公布日期 |
2001.02.13 |
申请号 |
US19990348736 |
申请日期 |
1999.07.06 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
SCHOENIGER SABINE;SCHROEGMEIER PETER;HEIN THOMAS;DIETRICH STEFAN;MARX THILO |
分类号 |
G11C11/408;G11C8/00;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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