| 摘要 |
The test circuit comprises a series circuit (DLY) with at least one type of circuit component, and a first and second verification circuit (4-6 ; 7-9, DLYC, DLYS), all of these circuits being prepared on the chip in the same process as a functional circuit. A series circuit is connected with its input to a test signal input (A) and with its output to an input in the first verification circuit (4-6) and one of the inputs in the second verification circuit (7-9, DLYC, DLYS), the other input being connected to an input in the first verification circuit. The output for the second verification circuit is connected to a test signal output (B). The first verification circuit generates an output signal for the second verification circuit when a test signal entering via the test signal input is delayed for at least a minimum time calculated on the basis of a first number of simulation models representing parameters that give the minimum delay in the test circuit. The second verification circuit generates an output signal for the test signal output when the output signal from the first verification circuit is present and the test signal is delayed by at most a maximum time calculated on the basis of a second number of simulation models representing parameters that give the maximum delay in the test circuit. |
