| 摘要 |
PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of a semiconductor device region even if an insulation gate field effect transistor is miniaturized by dividing only one adjacent electrode pattern while composing a semiconductor device for forming on the same layer as the other electrode and connecting one electrode to a wiring layer that is provided at another layer. SOLUTION: P and N channel MOSFETs 1 and 2 that become the load and drive parts of an inverter are formed. Then, a gate electrode 3, and a source diffusion layer 4 (4a) and a drain diffusion layer 5 that sandwich the gate electrode 3 are formed at the p-channel MOSFET 1. In this case, a silicide layer is formed on the diffusion layers, and the source diffusion layer 4 is connected to a source electrode 7 via a plurality of source contact holes 6. Then, a divided drain electrode 8 is formed on the drain diffusion layer 4 and a drain contact hole 9 is provided below it. The divided drain electrode 8 is connected to a silicide layer on the drain diffusion layer 5. A divided drain electrode 14 is formed on a drain diffusion layer 11 and is connected to the silicide layer via a contact hole 15.
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