| 摘要 |
PROBLEM TO BE SOLVED: To improve integration degree and to reduce size by forming a second well region selectively in an island shape into a first well region, arranging two chips at the second well region, and gluing the rear sides of the chips with a conductive adhesive. SOLUTION: A P-type well 23-2 and an N-type well 24-2 are formed in a large N-type well 22-2. An N-channel-type MOSFET1 is formed in the P-type well 23-2, and a low-potential power supply VSS is supplied. Also, the P-channel- type MOSFET1 is formed at the N-type well 24-2, and a high-potential power supply VCC that is the same as the large N-type well is supplied. Further, a P-type well 25-2 is formed in the large N-type well 22-2. An N-type well 26-2 and a P-type well 27-2 are formed in the P-type well 25-2, and a PMOS2 and an NMOS2 are formed in the N-type well 26-2 and the P-type well 27-2, respectively. The rear sides of the chips are glued and laminated. |
