| 摘要 |
PROBLEM TO BE SOLVED: To provide high speed access to both of a regular memory array and a redundant memory array by a look-ahead column redundancy circuit. SOLUTION: Both of information on an address bus and information on a next address bus are decoded by redundant column decoders 302, 303, address information of a decoder output is provided to a redundant column path. A DISABLE signal 315 of a decoder output is provided to a main column path. Information on an address bus is latched when it is started with a new column address. Information on a next address bus is latched for the next column address when it is operated by a burst cycle mode. When address information corresponds to an address in a redundant memory array 317, DISABLE is made active, and a main column selection circuit 307 is made invalid. When it does not corresponds to an address, as a column address is performed before being latched, memory access operation is performed in the main memory array without delay.
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