| 摘要 |
PROBLEM TO BE SOLVED: To improve stability against the fluctuation of the power supply voltage of a semiconductor memory device. SOLUTION: High potential side power wiring 3a is arranged so that they can cross digit lines DT and DB of an SRAM memory cell, and about half of the full parasitic capacities of the digit lines DT and DB is set as a wiring capacity Cvdd of the high potential side power source wiring 3a. Thus, it is possible to ensure the stability of the memory cell by holding relation between a threshold voltage Vth of an in-memory Cell CMOS inverter and the potential of the digital lines DT and DB in a high impedance state accompanied by the fluctuation of a power supply voltage. |
