发明名称 LAMINATED CHIP VARISTOR
摘要 <p>PROBLEM TO BE SOLVED: To obtain a laminated chip varistor, the varistor electrode and capacitance of which do not fluctuate much, when the varistor voltage is low. SOLUTION: The blank body of a laminated chip varistor is constituted, in such a way that an internal electrode connected to a first external electrode 7 and a counter electrode 3b connected to a second external electrode 8 facing opposite to each other with a gap G in between in the same plane. In addition, at least a part of an internal electrode 3a overlaps an internal electrode 4a which is connected to the second external electrode 8 via a varistor layer at different heights in the laminating direction Y.</p>
申请公布号 JP2001035707(A) 申请公布日期 2001.02.09
申请号 JP19990210162 申请日期 1999.07.26
申请人 TDK CORP 发明人 TANAKA RYUICHI
分类号 H01C7/10;(IPC1-7):H01C7/10 主分类号 H01C7/10
代理机构 代理人
主权项
地址