发明名称 INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To optimize a decoding speed corresponding to each of operating modes by performing different kinds of decoding respectively in various operating modes. SOLUTION: This circuit has a first decoder unit D1 and a second decoder unit D2 parallel connected thereto, each of two decoder units respectively has one input side to supply input signals A0...A2 to be decoded and (n) output sides, the relevant decoder unit makes (n) output sides active while depending on the input signals and decodes the input signals with various methods, the input side of the second decoder unit is connected to one input side of the first decoder unit D1, further, this circuit has (n) lines L1 to be selected, the line to be selected is connected with one output side of each of two decoder units and the potential of the line to be selected is detected through the output side by the first decoder unit in the first operating mode and by the second decoder unit in the second operating mode.
申请公布号 JP2001035163(A) 申请公布日期 2001.02.09
申请号 JP20000195059 申请日期 2000.06.28
申请人 INFINEON TECHNOLOGIES AG 发明人 DIETRICH STEFAN;SCHROEGEMEIER PETER;SCHOENIGER SABINE;WEIS CHRISTIAN
分类号 G11C11/408;G11C8/10;G11C11/401;G11C11/407;G11C11/413;(IPC1-7):G11C11/408 主分类号 G11C11/408
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