发明名称 MASTER/SLAVE TYPE FLIP-FLOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make transistor cascade connection between a power source and a ground in two steps, to operate it at a lower voltage and to enhance operation speed in a circuit structure by allowing all of clock differential amplifier, a master and slave flip-flop and a waveform reshaping amplifier to have a parallel connection with respect to a power source with the same phase. SOLUTION: This device is constituted of a clock differential amplifier INamp, a master/slave flip-flop MF/SF and a waveform shaping amplifier OUTamp, all of which are connected to a power source VCC in parallel, and these and composed of differential circuits 1 to 3 which fetch clock signals T and TB, input signal D and DD and an output signal of the MF respectively, data lines L1 and L2, and one to three dimensional charge setting circuits RL1 to 3 or outputs Q and Qb. The waveform shaping amplifier OUTamp performs waveform shaping by a differential circuit 4 and a final charge setting circuit RL4. Thus, the device and operate at high speed at a voltage of 2 V or smaller.
申请公布号 JP2001036389(A) 申请公布日期 2001.02.09
申请号 JP19990201908 申请日期 1999.07.15
申请人 MITSUBISHI ELECTRIC CORP;MITSUBISHI ELECTRIC ENGINEERING CO LTD 发明人 TAKAHASHI KOJI;INOUE TAKEO
分类号 H03K3/2885;H03K3/289;(IPC1-7):H03K3/289 主分类号 H03K3/2885
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