发明名称 SYSTEM AND METHOD FOR CLOCK PHASE AUTOMATIC ADJUSTMENT
摘要 PROBLEM TO BE SOLVED: To stably conduct automatic phase adjustment for a dot clock the being a sampling clock of analog video signals without being adversely affected by noise components of the signals. SOLUTION: A noise mask section 15 detects a maximum value of the fluctuation of digital signals in a blanking period of analog video input signals as a noise level value, determines a value that is not lower than the noise level value, as a mask signal value and masks noise components included in the digital signals by the mask signals. A phase detecting section 16 outputs a phase detection result based on the digital signals in which noise components are masked. A CPU 13 conducts a phase setting having several steps in a PLL circuit 14, stores the phase detection result of the phase of the circuit 14 at each step, determines the phase, at which the result becomes a maximum, as an optimum and sets the optimum phase in the circuit 14.
申请公布号 JP2001034222(A) 申请公布日期 2001.02.09
申请号 JP19990203753 申请日期 1999.07.16
申请人 NEC CORP 发明人 YAMASHITA TSUYOTOSHI
分类号 G09G3/36;G09G3/20;H03L7/08;H04N5/06;H04N5/12 主分类号 G09G3/36
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