SEMICONDUCTOR MEMORY DEVICE HAVING CIRCUIT TO LATCH DATA ON DATA LINE OF DATA OUTPUT PATH AND DATA LATCH METHOD OF THE DEVICE

摘要

PROBLEM TO BE SOLVED: To latch data to a data output register without loosing previous data by using the data latch signal which releases the data latch on a data line in response to a first rising interval of clock signals and latches the data on the data line in response to a second rising interval of the clock signals. SOLUTION: A data line control circuit 30 of a semiconductor memory device 2 generates first data latch signals FRP to latch data on a first data line FDIOi in response to column selection disable signals PCSLP, column addresses CAi and internal clock signals PCLKi. Thus, the signals FRP are activated in an effective data interval on the line FDIOi. Therefore, no data are lost while latching the data on the data line FDIOi of the data output path connected to first and second data output registers 40 and 42.