发明名称 WAFER LEVEL STACK PACKAGE AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To reduce a signal transmission path and to improve electrical conductivity by laminating two semiconductor chips at a wafer level for packaging. SOLUTION: In upper and lower semiconductor chips as upper and lower wafers 10 and 20, surfaces where bonding pads 11 and 21 are arranged are arranged at upper and lower parts with a specific interval. Then, lower insulation layers 40 and 41 are coated so that the bonding pads 11 and 21 are exposed to each semiconductor. Further, one end of upper and lower metal patterns 31 and 32 is connected to the bonding pads 11 and 21, and the metal patterns 31 and 32 are deposited onto the first insulation layers 40 and 41. At this time, the lower metal pattern 32 is formed longer than the upper metal pattern 31. A solder ball 90 is mounted to the pattern film for packaging.
申请公布号 JP2001035998(A) 申请公布日期 2001.02.09
申请号 JP20000185762 申请日期 2000.06.21
申请人 HYUNDAI ELECTRONICS IND CO LTD 发明人 KIN SAIBEN
分类号 H01L23/12;H01L21/98;H01L23/13;H01L25/065;H01L25/07;H01L25/18;H04R1/10;(IPC1-7):H01L25/065 主分类号 H01L23/12
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