| 摘要 |
A digital signal processor device (10) includes a data cache (11); a scalar arithmetic unit (26) coupled to the data cache; and a parallel processing unit (20) coupled to the data cache, where the parallel processing unit includes an n row by m column array of parallel arithmetic units (23), and n pattern matcher coprocessors (24) individual ones of which are coupled to one of said n rows of parallel arithmetic units. The device can be programmed using one-dimensional and two-dimensional parallel data types, and a program for the device can be made using a method that defines an amount of parallelism, and then using a compiler to produce code having the same amount, or a lesser amount, of parallelism than used to define the program. |
