发明名称 DATA TRANSFER CONTROLLER AND ELECTRONIC EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To prevent stall, etc., of firmware processing due to generation of reset by distinguishing whether a received packet is a packet received at different reset intervals or not and writing each received packet and each generated distinguishing information in a packet storage means by relating each packet to each distinguishing information. SOLUTION: A RAM 80 by which random access is enabled and to store the packet, buses 90, 95, 99, 100 to be mutually separated and a mediation circuit 74 to connect the buses with a bus 110 of the RAM 80 are provided. An interval from one bus reset and the next bus reset is defined as a bus reset interval. The interval from the bus reset M to M+1 becomes the reset interval of M and the interval from the bus reset M+1 to M+2 becomes the bus reset interval M+1. Whether the received packet or the packet received next is the one received by different reset interval or not is distinguished.
申请公布号 JP2001036531(A) 申请公布日期 2001.02.09
申请号 JP19990201248 申请日期 1999.07.15
申请人 SEIKO EPSON CORP 发明人 ISHIDA TAKUYA;KANBARA YOSHIYUKI
分类号 G06F13/38;G06F13/00;H04L12/28;H04L12/407;H04L12/64;H04L13/08;(IPC1-7):H04L12/28 主分类号 G06F13/38
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