Synchronous data scanning circuit for sequential data input, has data units scanned at the edge of the first pulsed signal generated during a clock-pulse interval at a low logic

摘要

Improved efficiency of synchronous data scanning circuits as required for operation in dual data rates (DDR)-DRAMs and Rambus-DRAMs which operate at high working frequencies required circuits capable of scanning several data units during a clock signal cycle, with a circuit based on two pulsed signal generators (31,32) and four scanning units(33-36), for receiving the clock-pulse signal and scanning the sequentially input (DQ) data, and the outputting (DIO) the data, respectively.