| 摘要 |
A programmable logic device includes a node and a RAM cell configured to power-up in a preferred state so as to provide a predetermined logic signal to the node upon power-up. The node may comprise an interconnection element, for example a transistor. Associated with the interconnection element may be two signal lines within the programmable logic device, for example, as part of a programmable interconnect matrix. The interconnection element and the two signal lines are associated such that when the interconnection element is in a first state the two signal lines are electrically coupled and when the interconnection element is in a second state the two signal lines are not electrically coupled. The predetermined logic signal from the RAM cell selects one of the first and second states. The RAM cell may include two PMOS transistors, each having an associated threshold voltage, wherein the threshold voltage of one of the PMOS transistors is lower than the threshold voltage of the other PMOS transistor. The RAM cell may be included in a look-up table such that the node is an output of the look-up table. Alternatively, the programmable logic device may further include a multiplexer wherein the RAM cell is coupled to the data path input of the multiplexer through the node. In other embodiments, the RAM cell may act as a select cell for the multiplexer.
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