| 摘要 |
A test system for testing a semiconductor device by having a number of test channels (tester pins) corresponding to the number of terminal pins of the semiconductor device to be tested includes: a tester controller for controlling various operations in the tests system including test patterns to be applied to the device under test, timings and waveforms of the test patterns; a test unit for generating the test patterns and expected value patterns with predetermined timings based on control signals from the tester controller; a pin assignment converter provided between the tester controller and the test unit for providing conversion data showing a conversion relationship between physical pin numbers of the test unit and supplemental tester pin numbers which have been replaced with defective tester pins to the test unit; a test head having drivers for supplying the test patterns from the test unit to the semiconductor device with predetermined amplitudes and comparators for detecting levels of output signals from the semiconductor device and comparing the output level with the expected value; a switch circuit provided between the test head and the semiconductor device for changing the defective tester pin to the supplemental tester pin based on the conversion data from the pin assignment converter; and a system monitor for monitoring the change in the tester pins in the test system and other changes involving maintenance works and managing the data thereof.
|
