| 摘要 |
The invention provides a circuit for precisely measuring a retention time of a memory cell of a DRAM. The circuit includes at least includes a DRAM memory cell and a periphery MOS device. The DRAM memory cell includes, for example, an N-type MOS (NMOS) transistor with a capacitor. The NMOS transistor has a source region coupled to a lower electrode of the capacitor, a drain region coupled to a first voltage, and a gate electrode coupled to a second voltage. The capacitor is also coupled to a third voltage at its upper electrode. The periphery MOS device includes a gate electrode coupled to the NMOS transistor at a node between the NMOS transistor and the capacitor. A drain region of the periphery MOS device is coupled to a fourth voltage, and a source region of the periphery MOS device is coupled to a fifth voltage. Moreover, the circuit includes another periphery MOS device, which is coupled to the previous periphery MOS device in parallel, but the gate electrode of the periphery MOS device is coupled to a sixth voltage.
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