发明名称 Method for minimizing warp in the production of electronic assemblies
摘要 The present invention relates to assembly techniques and the resulting products which are thermally stable, have high structural integrity, and compensate for thermal stresses that occur between the various components of the package. This is accomplished, in-part, by designing the package so that the coefficient of thermal expansion (CTE) of a stiffening ring which is mounted on the package substrate matches the CTE of the substrate and optional lid. Further, the particular adhesives used to bond the stiffening ring are chosen to match their CTE to that of the substrate, ring and lid. Moreover, the substrate is designed so that its CTE, at least in-part, matches that of the chip, and also that of the stiffening ring.
申请公布号 US6183592(B1) 申请公布日期 2001.02.06
申请号 US19980196874 申请日期 1998.11.20
申请人 SYLVESTER MARK F. 发明人 SYLVESTER MARK F.
分类号 H01L23/373;H01L23/498;H05K1/00;H05K1/02;H05K1/18;(IPC1-7):B32B31/00 主分类号 H01L23/373
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