| 摘要 |
One multiplier 13 operated at a normalized frequency 4 is provided to multiply the elements of DCT transformation coefficients and the elements of input data, and the multiplication results are added by a cumulative adder 15 to determine cumulative addition results corresponding to the sum (x0+x7) and the difference (x0-x7) of a pair of elements (x0, x7) of data to be outputted from a one-dimensional DCT operation circuit 1. The paired cumulative addition results are added and subtracted by an adder 17 and a subtracter 18, respectively, to determine the elements (x0, x7). The operations are performed specific times the number of which is one half of the number of elements of a column of the matrix of the input data to determine the elements of a column of the matrix of the output data and are performed specific times the number of which is equal to the number of elements of a row of the matrix or the input data to determine all the elements of the matrix of the output data. As a result, the scale of the DCT operation circuit is reduced, thereby reducing the power consumption.
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